DS21Q55DK【PDF 8/32 页】KIT DESIGN FOR DS21Q55

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DS21Q55DK Quad T1/E1/J1 Transceiver Design Kit

CONTROL REGISTERS

Register Name: MCSR

Register Description: DS21Q55 MCLK Pin Source

Register Offset: 0x0011

Bit #

Name

Default

7

—

—

6

—

—

5

—

—

4

—

—

3

—

—

2

—

—

1

MSRCB

1

0

MSRCA

1

Bit 0: DS21Q55 Port 1 and 3 MCLK Source (MSRCA)

0 = Connect MCLK 1 (controls port 1 and 3) to the 1.544MHz clock

1 = Connect MCLK 1 (controls port 1 and 3) to the 2.048MHz clock

Bit 1: DS21Q55 Port 2 and 4 MCLK Source (MSRCA)

0 = Connect MCLK 2 (controls port 2 and 4) to the 1.544MHz clock

1 = Connect MCLK 2 (controls port 2 and 4) to the 2.048MHz clock

Register Name: TCSR

Register Description: DS21Q55 TCLK Pin Source

Register Offset: 0x0012

Bit #

Name

Default

7

T4S1

0

6

T4S0

0

5

T3S1

0

4

T3S0

0

3

T2S1

0

2

T2S0

0

1

T1S1

0

0

T1S0

0

Bit 0 to 1: DS21Q55 Port 1 TCLK Source (T1S0, T1S1)

The source for TCLK 1 is Defined as shown in Table 3.

Bit 2 to 3: DS21Q55 Port 2 TCLK Source (T2S0, T2S1)

The source for TCLK 2 is Defined as shown in Table 3.

Bit 4 to 5: DS21Q55 Port 3 TCLK Source (T3S0, T3S1)

The source for TCLK 3 is Defined as shown in Table 3.

Bit 6 to 7: DS21Q55 Port 4 TCLK Source (T4S0, T4S1)

The source for TCLK 3 is Defined as shown in Table 3.

Table 3. TCLKx Source Definition

TxS1, TxS0

00

01

10

11

TCLK CONNECTION

Drive TCLK X with the 1.544MHz clock

Drive TCLK X with the 2.048MHz clock

Drive TCLK X with RCLK X

N/A

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